The present invention relates to a method for manufacturing FET (Field Effect Transistor) and, more particularly, to a method for manufacturing FET having a fine gate on the order of submicrons. Such FET is used as a constituent element of semiconductor integrated circuit.
Conventionally, for example, CMOSLSI (Complementary Metal-Oxide Semiconductor Large-Scale Integrated circuit) having polycrystalline silicon gate is manufactured generally by a process flow as shown in FIG. 5. First, ion implantation is performed to form necessary wells on a semiconductor substrate (S101), and device isolation regions for isolating MOS transistors to be formed, from one another, is formed (S102). Next, ion implantation for adjusting the threshold value Vth of N-channel MOS transistor or P-channel MOS transistor and for preventing punchthrough is performed (S103). Next, after gate oxide is formed, polycrystalline silicon is deposited all over the substrate, and the polycrystalline silicon is processed by photolithography and etching, by which gate electrodes is formed (S104). Subsequently, measurement of gate length (line width measurement) is performed (S105). A result of this gate length measurement, i.e., a xe2x80x9cshiftxe2x80x9d of gate length measured value of one lot from a target gate length is fed back to photolithography conditions and etching conditions for succeeding lots so that the gate length of succeeding lots becomes the target gate length (a control route therefor is shown by arrow F in FIG. 5). Next, with the gate electrode used as a mask, LDD (Lightly Doped Drain) implantation and halo-implantation are performed, by which LDD region and halo-implantation region are formed in both-side regions of the gate electrode (S106). Subsequently, side wall made of SiO2 is formed on the side faces of the gate electrode, and source/drain implantation is performed with the gate electrode and the side walls used as a mask, by which source/drain region of high impurity concentration is formed at regions away from the gate electrode by a distance generally corresponding to the thickness of the side wall (S107). After this, an interlayer insulator is deposited all over the substrate, and heat treatment for activating the implanted impurities is performed. Then, contact windows are formed and wiring electrodes are formed (S108).
As is well known, in MOS transistor having a gate length shorter than 1 xcexcm, the channel effect becomes prominent so that variations in machining dimensions of the gate length largely affect the transistor characteristics (such as threshold voltage Vth, drain current Ids, drain withstand voltage BVds, etc.). For example, as shown in FIG. 3, as the drain current IdsPch of the P-channel transistor increases, the number of defective chips increases. Due to this, in the manufacturing process of MOS transistor having a gate length of the order of submicrons, it is of great importance to control the gate length. For this reason, as described above, a result of measuring the gate length of one lot is fed back to the photolithography conditions and etching conditions of succeeding lots.
Under the present circumstances, however, since the dimensional accuracy has reached to a limit even with the use of the state-of-the-art stepper, there is a possibility that the gate length of the lot may fall outside the permissible range (so-called specifications, which are previously set, for example, as +0.020 xcexcm for a target gate length of 0.300 xcexcm) due to weather conditions or the like. If the gate length of a lot falls outside the permissible range by the prior art manufacturing method, in which a step of determining or adjusting the transistor characteristics (Vth, Ids etc.) relating to the short-channel effect is involved before the step of gate electrode formation, there would inevitably occur lot rejection or yield lowering and, moreover, production efficiency (production output per unit time) lowering.
Therefore, an object of the present invention is to provide a method for manufacturing FET which is capable of successfully controlling transistor characteristics relating to the short-channel effect even if the gate length has varied to some extent in the step of gate electrode formation.
The present invention has been achieved based on a conception that for the process of manufacturing MOS transistor having a gate length of 0.40 xcexcm or less, more prominently 0.35 xcexcm or less, transistor characteristics relating to the short-channel effect can be controlled by changing the dose (implantation amount) for source and drain implantation.
That is, in the process of manufacturing MOS transistor having a gate length of about 0.4 xcexcm to 0.5 xcexcm or less, changing the gate length to such an extent as to cause changes in the transistor characteristics relating to the short-channel effect (changes of about 0.01 xcexcm) would entail a need for changing the dose (implantation amount) for source and drain implantation about 0.5 to 3 folds. Such a large change in the dose for source and drain implantation would have a considerable influence on not only the transistor characteristics relating to the short-channel effect but also the contact resistance and the parasitic capacitance of the source/drain region. On this account, the idea that the transistor characteristics are controlled by changing the dose for source/drain implantation has never been provided so far.
However, the present inventor assumed that transistor characteristics relating to the short-channel effect could be controlled by changing the dose for source/drain implantation without adversely affecting the other transistor characteristics, and demonstrated the conception, when the target gate length becomes 0.40 xcexcm or less, more prominently 0.35 xcexcm or less.
Therefore, according to the present invention, there is provided a method for manufacturing a field effect transistor including the steps of forming a gate electrode having a gate length of 0.4 xcexcm or less on a semiconductor substrate, and subsequently forming a source region and a drain region on a substrate surface on both sides of the gate electrode, respectively, the method further comprising the step of: with a gate length of the gate electrode measured, setting a dose of ion implantation for forming the source region and the drain region variably according to a measured value of the gate length so that transistor characteristics relating to short-channel effect of the field effect transistor to be formed are controlled to a specified level.
It is noted here that the terms, xe2x80x9ccharacteristics relating to the short-channel effect,xe2x80x9d refer to characteristics that depend on the gate length such as threshold voltage Vth and drain current Ids.
In the method for manufacturing FET according to the present invention, a gate electrode having a gate length of 0.4 xcexcm or less is formed on a semiconductor substrate. The gate length of this gate electrode is measured, and the dose of ion implantation for forming the source region and the drain region is set variably according to the gate length measured value. As a result of this, even if the gate length has varied to some extent in the step of gate electrode formation, the characteristics relating to the short-channel effect of FET to be formed can be controlled to a specified level. Accordingly, rejection of lots in the semiconductor manufacturing process can be avoided, so that yield and production efficiency can be enhanced.
More specifically, when the gate length measured value is larger than the target gate length, the dose of ion implantation for forming the source region and the drain region is set so as to be increased, and when the gate length measured value is smaller than the target gate length, the dose of ion implantation for forming the source region and the drain region is set so as to be decreased. When the dose of ion implantation for forming the source region and the drain region is increased, lateral diffusion of the source region and the drain region is increased and shifted in such a direction that the gate length is effectively decreased. On the other hand, when the dose of ion implantation for forming the source region and the drain region is decreased, the lateral diffusion of the source region and the drain region is decreased and shifted in such a direction that the gate length is effectively increased. As a result of this, variations of the gate length in the gate electrode formation step are substantially canceled, by which the characteristics relating to the short-channel effect of FET can be controlled to a specified level.
Further, a method of changing the dose of LDD (lightly doped drain) implantation and/or halo implantation (or pocket implantation) to be performed after the gate electrode formation step could also be conceived. However, in such cases, the transistor characteristics relating to the short-channel effect are so considerably changed as to be difficult to stably control. On the other hand, when the dose of ion implantation for forming the source/drain region of high impurity concentration, the transistor characteristics relating to the short-channel effect become so stable as to be gently changed.
Further, a method of changing the lateral diffusion amount of the source/drain region is changed by changing the annealing conditions after the source/drain implantation could also be conceived. However, for the setting of annealing conditions, it is practically difficult to finely control the lateral diffusion amount. On the other hand, the dose of ion implantation is set at high accuracy by normal functions of ion injectors (with Faraday cups or the like). It follows accordingly that a method of variably setting the dose of ion implantation for forming the source/drain region should be adopted as in this invention.
In an embodiment, the field effect transistor is a P-channel transistor; and the dose of ion implantation for forming the source region and the drain region is set to 2.5xc3x971015 atms/cm2 when the gate length measured value is coincident with a target gate length, and changed within a range from 1.6xc3x971015 atms/cm2 to 3.4xc3x971015 atms/cm2 when the gate length measured value is not coincident with the target gate length.
With the method for manufacturing FET according to this one embodiment, even if the gate length has varied to some extent in the step of gate electrode formation, the characteristics relating to the short-channel effect of P-channel transistor is controlled to a specified level. Still, various transistor characteristics other than the characteristics relating to the short-channel effect are not adversely affected.
Also, in an embodiment, the field effect transistor is an N-channel transistor; and the dose of ion implantation for forming the source region and the drain region is set to 2.4xc3x971015 atms/cm2 when the gate length measured value is coincident with a target gate length, and changed within a range from 1.5xc3x971015 atms/cm2 to 4.0xc3x971015 atms/cm2 when the gate length measured value is not coincident with the target gate length.
With the method for manufacturing FET according to this one embodiment, even if the gate length has varied to some extent in the step of gate electrode formation, the characteristics relating to the short-channel effect of N-channel transistor is controlled to a specified level. Still, various transistor characteristics other than the characteristics relating to the short-channel effect are not adversely affected.
More specifically, first, Table 1 given below shows ranges of drain current IdsPch (unit: xcexcA/xcexcm) of P-channel MOS transistor (hereinafter, referred to as xe2x80x9cP-channel transistorxe2x80x9d), ranges of drain current IdsNch (unit: 82A/xcexcm) of N-channel MOS transistor (hereinafter, referred to as xe2x80x9cN-channel transistorxe2x80x9d), and tolerances of gate length (unit: xcexcm), when the target gate length is 1.00 xcexcm, 0.50 xcexcm, 0.40 xcexcm, 0.35 xcexcm, 0.30 xcexcm, 0.25 xcexcm and 0.20 xcexcm, respectively. As to the target threshold voltages, VthNch=0.5 to 0.6 (V), VthPch=xe2x88x920.5 to xe2x88x920.6 (V). In addition, the drain currents IdsPch and IdsNch are specified in volume for a channel width of 1 xcexcm.
Target threshold voltage:
VthNch=0.5 to 0.6 (V), VthPch=xe2x88x920.5 to xe2x88x920.6 (V)
Next, Table 2 shows data of dose changes (unit: atms/cm2) required to change the drain current IdsPch of P-channel transistor by 10 xcexcA/xcexcm, and data of gate length shift amounts (unit: xcexcm) that cause IdsPch to change by 10 xcexcA/xcexcm, when the target gate length is 1.00 xcexcm, 0.50 xcexcm, 0.40 xcexcm, 0.35 xcexcm, 0.30 xcexcm, 0.25 xcexcm and 0.20 xcexcm, respectively. In this case, the conditions for ion implantation of the source/drain region of P-channel transistor is an ion species of BF2+, an accelerating energy of 25 keV and a dose median of 2.5xc3x971015 atms/cm2.
For instance, with respect to P-channel transistor having a gate length of 0.30 xcexcm, which is today""s mainstream, it can be seen from correlation data between IdsPch and gate length (measured values) shown in FIG. 4 that when the gate length has changed by 0.01 xcexcm, the drain current IdsPch changes by 12 xcexcA/xcexcm. Like this, the values in Table 2 were determined based on actually measured correlation data (however, data on the target gate lengths of 1.00 xcexcm and 0.50 xcexcm are ones estimated by extrapolation, which is also applicable to Table 3).
Similarly, Table 3 shows data of dose changes (unit: atms/cm2) required to change the drain current IdsNch of N-channel transistor by 10 xcexcA/xcexcm, and data of gate length shift amounts (unit: xcexcm) that cause IdsNch to change by 20 xcexcA/xcexcm, when the target gate length is 1.00 xcexcm, 0.50 xcexcm, 0.40 xcexcm, 0.35 xcexcm, 0.30 xcexcm, 0.25 xcexcm and 0.20 xcexcm, respectively. In this case, the conditions for ion implantation of the source/drain region of N-channel transistor is an ion species of As+, an accelerating energy of 20 keV and a dose median of 2.4xc3x971015 atms/cm2.
Conditions for ion implantation of P-channel source/drain region: ion species of BF2+; accelerating energy of 25 keV; and dose median of 2.5xc3x971015 atms/cm2.
Conditions for ion implantation of N-channel source/drain region: ion species of As+; accelerating energy of 20 keV; and dose median of 2.4xc3x971015 atms/cm2.
Table 4 shows dose ranges (unit: atms/cm2) that cover the ranges of the drain currents IdsPch and IdsNch shown in Table 1 in correspondence to the correspondence between the changes in IdsPch, IdsNch and dose changes shown in Tables 2 and 3, when the target gate length is 1.00 xcexcm, 0.50 xcexcm, 0.40 xcexcm, 0.35 xcexcm, 0.30 xcexcm, 0.25 xcexcm and 0.20 xcexcm, respectively. In this case, the conditions for ion implantation of the source/drain region of P-channel transistor and N-channel transistor are the same as in Tables 2 and 3, respectively.
As can be understood from this Table 4, when the target gate length is 0.40 xcexcm or less, the dose setting range for source/drain implantation becomes a practical level.